The Post-Quantum Migration Reaches the Silicon Layer
Quentir Defense Monitor
Evidence-based insights for quantum defense and security. Published by Quentir Systems LLC · August 16, 2026.
In the same August week, on opposite sides of the Pacific, two teams announced working silicon for the cryptography that is meant to survive a quantum computer. In Wuhan on August 14, Huazhong University of Science and Technology and the Hubei security firm Xin'antong released the ECQP-50GP, a security chip fabricated on a 28-nanometer process that runs the NIST-standardized post-quantum algorithms alongside the classical ciphers they will eventually replace. Days earlier, Canada's BTQ Technologies and Taiwan's Industrial Technology Research Institute reported that their compute-in-memory architecture for the same algorithm family had passed functional validation in a TSMC 28-nanometer design environment, with test chips promised to partners by the end of the year.
The two announcements are unconnected, and they rhyme. For two years the story of post-quantum cryptography has mostly been a software story: new handshakes in browsers, migration inventories in banks, advisories telling agencies to count their certificates. Both of this week's announcements aim at the layer underneath all of that, the hardware where keys are stored, firmware is checked and identities are anchored. That layer changes slowly, ships inside platforms that serve for decades, and is exactly where a defense buyer's exposure lives longest. Two independent supply chains reaching it in the same week is worth a briefing.
A chip release with a naval research institute in the room
The Wuhan announcement came at a regional cybersecurity summit, and the details in the Hubei Daily report reward a careful read. The ECQP-50GP was developed by the team of Professor Liu Dongsheng at the university's School of Integrated Circuits and released jointly with Hubei Xin'antong, which has already completed a line of cryptographic cards and cryptographic modules built on the chip. The part is fabricated on a 28-nanometer process, supports NIST-standardized post-quantum algorithms together with classical ones, uses a dedicated RISC-V instruction set and carries what the report calls an operator-level reconfigurable design, meaning the building blocks of its cryptographic engines can be rearranged after fabrication.
Each of those choices says something. A Chinese university chip implementing the American NIST standards, rather than waiting for China's own post-quantum selection to conclude, tells you which algorithm family its designers expect the world's traffic to actually use. The mature 28-nanometer node is cheap, well characterized and available from several foundries, including domestic ones, which matters for a part meant to sit in infrastructure for a long time. And the reconfigurability is a hedge: cryptographic standards can shift after silicon ships, and a fixed-function engine in a fielded system is a liability the moment an algorithm falls.
The room itself carried a signal. The summit ran with support from the 722 Research Institute of the China State Shipbuilding Corporation, the Wuhan institute responsible for naval communications research, alongside the industry alliance of the National Cybersecurity Base, the talent and innovation campus that already hosts more than four hundred companies. A commercial chip launch attended by a naval communications institute, inside a national base built to convert university research into fielded security products, is a fair picture of how China intends post-quantum hardware to move from laboratory to platform.
Crypto-agility, written into hardware this time
The other announcement is earlier on the same road. In a release this month, BTQ Technologies and ITRI reported validating the core of their Quantum Compute-in-Memory architecture, QCIM, in a TSMC 28-nanometer design environment, exercising the three algorithms at the heart of the NIST post-quantum framework. Those are the algorithms of FIPS 203, the module-lattice key-encapsulation standard finalized in August 2024, and its companion signature standards FIPS 204 and 205. The Korean secure-semiconductor firm ICTK contributes physical unclonable function technology for device authentication, ITRI the design and validation muscle, BTQ the cryptographic architecture.
The architectural bet is different from Wuhan's and aimed at the same fear. As reporting on the milestone explains, QCIM performs cryptographic operations inside the memory subsystem instead of shuttling data between storage and a separate compute unit. Every transfer it eliminates saves power and latency and removes a surface where power and timing analysis can watch keys move. The lattice algorithms are hungrier than the RSA and elliptic-curve arithmetic they replace, and long-life embedded devices, the radios and sensors and vehicle controllers that run on tight power budgets, are precisely where that hunger hurts. BTQ describes the design as crypto-agility in silicon: new algorithms can be loaded without new fabrication, the same hedge Wuhan built through reconfigurable operators.
Company chief executive Olivier Roussy Newton framed the target plainly: organizations will require hardware that delivers stronger cryptographic protection without unacceptable performance, power or deployment constraints. The named markets include military systems, industrial equipment, automotive platforms and connected infrastructure, with module-level integration next and test chips shipping to partners by the end of 2026.
Quantum pillar: post-quantum cryptography (roots of trust in hardware). Use posture: defensive. Technology readiness: TRL 4 of 9. The Wuhan chip exists as fabricated 28-nanometer silicon already assembled into cryptographic cards and modules and exercised under laboratory conditions, while public evidence of realistic network trials, independent evaluation or operational fielding does not yet exist for it, and the rival QCIM architecture sits a rung lower as a design validated in simulation ahead of its first test silicon.
What a post-quantum root of trust lets a force keep
A root of trust is the piece of hardware a platform consults when it decides which firmware to boot, which update to accept and which device on the network to believe. On a frigate, a tanker aircraft or a satellite, that silicon serves for thirty years or more, which means the cryptography burned into it will outlive several eras of cryptanalysis. Today those anchors rest on RSA and elliptic curves. A quantum computer large enough to run Shor's algorithm would let an adversary forge exactly the signatures that gate firmware loading, and at that point every fielded modem, radio and engine controller with an unpatchable anchor becomes a possible entry point. Replacing the anchor is slow precisely because it is hardware, which is why program offices need to see parts like these years before the threat matures.
The capability reading is defensive in the plain sense of the capability map. A post-quantum hardware anchor lets a force keep three things it already owns. It keeps recorded traffic confidential against the harvest-now-decrypt-later collector, the adversary recording ciphertext today to read once quantum machines arrive, since lattice key exchange denies that future payoff. It keeps the firmware supply chain trustworthy, because signature checks in silicon survive the fall of the classical schemes. And it keeps device identity meaningful across a fleet of sensors and effectors whose authentication would otherwise age out with the mathematics. Nothing in either announcement points at an attacking capability; the same part protects a bank and a frigate, and both announcements name both customers.
Who gains is a question about supply chains as much as physics. What this week shows is two of them maturing in parallel: a Chinese chain running from a university integrated-circuit school through a provincial company into a national cybersecurity base with naval research in the room, and a Canada-Taiwan-Korea chain aimed at NIST validation and TSMC production for allied markets. Defense buyers on each side will only ever field parts from their own chain, so the meaningful competition is over readiness dates, and each side now has a public one to beat.
The distance between a launch event and a program office
Everything above rests on the parties' own claims, and a buyer should price that in. Neither announcement publishes throughput or power figures, neither reports an independent side-channel evaluation, and the history of cryptographic hardware says that is where the hard work starts: lattice implementations leak through power and timing until they are carefully masked, and evaluation laboratories exist because vendor functional testing misses exactly those channels. The regulatory gates are also still ahead. A part like the ECQP-50GP faces China's commercial cryptography evaluation regime before government systems may carry it, and a QCIM-based module faces FIPS 140-3 validation before an American program office may buy it. Reconfigurability, the feature both teams advertise, historically makes those evaluations harder rather than easier, since an engine that can become many circuits must be evaluated as all of them.
The readiness picture is therefore early and legible. Fabricated silicon assembled into cards and modules and exercised in the laboratory places the Wuhan part at the validated-in-the-lab rung, with realistic trials, national evaluation and fielding all still ahead of it. A design proven in a process design environment with test chips promised for year-end sits a rung below. The signals worth watching over the next two years are public performance data, completed national evaluations on either side, a design win inside a named defense program, and whether China's own post-quantum standardization effort changes what Chinese silicon carries. The sources establish that post-quantum cryptography has crossed from standards documents into silicon on both sides of a strategic divide, with defense customers explicitly in view. They establish nothing yet about protection delivered in the field, and a program office should hold both statements at once.
Sources
Primary source: Jingchu.com (Hubei Daily network) correspondent Liu Yueheng on the release of the ECQP-50GP chip by Professor Liu Dongsheng's team at Huazhong University of Science and Technology and Hubei Xin'antong, August 16, 2026, via China.com Hubei. Supporting material from the BTQ Technologies and ITRI press release on the QCIM milestone, NIST's FIPS 203 standard, and TechJuice's reporting on the QCIM compute-in-memory architecture.