Fault-tolerant quantum machines

Google’s Willow chip demonstrated below-threshold surface-code scaling: logical error rates fell as the code grew. AI joined the control loop — AlphaQubit outperformed leading matching and tensor-network decoders in published tests. A neutral-atom processor has run algorithms on up to 48 logical qubits. A 2026 architecture study cut the resource estimate for Shor’s algorithm to as few as ~10,000 reconfigurable atomic qubits, and independent work cut the estimated qubit count for factoring RSA-2048 from twenty million to under one million. In July 2026 IBM and the University of Chicago ran an encoded sampling circuit on 70 logical qubits through 2,415 logical two-qubit gates, holding logical error rates ten times below the physical rates and proving the fidelity of the run. HRL Laboratories ran error correction on an 18-qubit silicon spin processor with every control signal generated inside the refrigerator, and errors fell by roughly a factor of five as the code grew. Three peer-reviewed hardware results extended the line in July and August 2026. D-Wave and Yale demonstrated an entangling gate for dual-rail erasure qubits with hardware-level erasure detection, running in about 500 nanoseconds at a Pauli error rate below 0.1% per gate, with bit-flip errors suppressed to about one in a million. Quantinuum, the University of Chicago, Harvard and Stony Brook prepared a 54-qubit non-Abelian ground state on the H2 trapped-ion processor and realized a universal topological gate set by braiding and fusing anyons, encoding logical qutrits in the fusion space of separated anyons. An Imperial College London team joined programmable linear-optical networks to integrated nonlinear modules and generated optical Gottesman–Kitaev–Preskill states quasi-deterministically at roughly 2,000 states per second, a bosonic error-correction resource that earlier optical experiments produced only probabilistically.